1. Field of the Invention
The present invention relates to the field of data communications circuits; more specifically, it relates to a clock and data recovery circuit and a phase adjustable clock circuit.
2. Background of the Invention
In clock and data recovery circuits (CDRs) for data communication streams operating at very high speeds clock signal noise and other circuit induced noise can result in increased data bit error rates. Examples of bit errors include zeros being reconstructed as ones and ones being reconstructed as zeros.